Semiconductor devices, such as dynamic random access memory (DRAM) devices, undergo a tremendous amount of testing at various steps in the production process. Moreover, many memory devices include self-test arrangements for determining that the memory device is functioning properly. Typically, DRAM devices are tested by using write and read operations to determine whether all of the cells of the memory array can properly store data signals and whether the data signals can be read out of the memory array. As memory chips become more dense, the testing time that is required to verify that data is being correctly stored and read out has increased dramatically.
In one test that is commonly used to identify faulty cells of a memory array, a signal having a logic level of either one or zero is applied to one group of the memory cells and signals of the opposite logic level are applied to the remaining cells. The signals are then read out of the cells individually and tested for the correct logic levels. This test must be repeated for each of the cells in the memory array and the entire procedure is repeated with signals of the opposite logic levels. Consequently, testing an array of memory cells requires a substantial amount of time.
Currently, predetermined data patterns are loaded, or sequenced through the memory as controlled by an external tester. Advanced testing procedures have used a row copy function to speed up testing. An example of a row copy function that can be used in testing of a memory is disclosed in U.S. Pat. No. 5,440,517. In such arrangements, a pattern of data bits is written to a memory array row using an external memory tester, and the data thus stored is copied to some or all of the other rows of the memory for programming the memory to a bit pattern desired for testing.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a test arrangement that allows testing of memory devices, wherein the time required for conducting the testing is minimized and wherein space requirements on the memory chip for implementing the test arrangement are minimized.